1. Field of the Invention
This invention relates to a semiconductor memory device and in particular, to a non-volatile semiconductor memory device capable of simultaneous writing of a plurality of bytes.
2. The Related Art
A non-volatile semiconductor memory device for simultaneous writing of a plurality of bytes, as disclosed in Japanese Laid-open Patent No. Hei 5-159586, is shown in FIG. 8. The memory device comprises a memory cell array 1 which includes writable and erasable memory cells M00-M33 arranged in rows and columns in a matrix. A plurality of bit lines BL0-BL3 are connected to the drains of the memory cells arranged in rows corresponding to memory cells M00-M33. The memory cell array 1 contain a plurality of word lines WL0-WL3 connected to the control gates of the memory cells arranged in lines corresponding to memory cells M00-M33. A Y decoder 2 decodes the address signal to select one of bit lines BL0-BL3. A Y selector 3 comprises N channel MOS transistors NY0-NY3 whose gates are input with the output of the Y decoder 2 installed to correspond to the bit lines BL0-BL3. An X decoder 4 decodes the address signal to select one of word lines WL0-WL3. A sense amplifier 5 reads out the data stored in the memory cells selected with the Y decoder 2, the Y selector 3 and the X decoder 4. Write circuits LA0-LA3 each include a respective latch for latching data from a data line 6 and outputting a write voltage to write data on the memory cells based on data input from the latches.
As shown in FIG. 9, the write circuits LA0-LA3 are each comprised of a transfer gate, made up of an N channel MOS transistor 2, which is connected between a latch 7 and the data line 6 and which is responsive to the address Y. The latch 7 comprises a transfer gate made up of inverters 64 and 65, an N channel MOS transistor 53 and a P channel MOS transistor 54 for feedback when the latch signal DL is LOW. The latch 7 also comprises a transfer gate made up of an N channel MOS transistor 51 and a P channel MOS transistor 52 for conducting when the latch signal DL is HIGH. The write circuits LA0-LA3 are comprised of a transfer gate made up of N channel MOS transistor 55 and a P channel MOS transistor 56 for conducting when the write signal PRO is HIGH. The write circuits also include an inverter comprised of an N channel MOS transistor 59 and a P channel MOS transistor 58 connected serially between ground voltage (GND) and a program high voltage power supply Vpp wherein the inverter inputs the output from the transfer gate controlled by the write signal PRO. Additionally the write circuits include a P channel MOS transistor 57 connected at its source to the power supply Vpp, at its gate to the output of the inverter, and at its drain to the input of the inverter. An N channel MOS transistor 60 is also included in the write circuits to pull down the input of the inverter when the write signal PRO0 is LOW. The write circuits also include an N channel MOS transistor 61 whose source is connected to the bit line BL, whose gate is connected to the output of the inverter, and whose drain is supplied with a voltage VH to write the necessary data on the memory cell.
FIG. 11A show an example of a memory cell according to FIG. 8 and FIG. 11B show operation methods for erasing, writing and reading of the memory cell. To effect erasure in the memory cell, for instance, the voltage shown in FIG. 11B is applied, thereby causing electrons to be injected into a floating gate 11 from a p channel substrate 10 by means of the F-N tunnel mechanism so that the memory cell threshold voltage shifts to a high value (for instance 6 volts). However during write, the electrons are pulled from the floating gate 11 to the p channel substrate 10 by means of the F-N tunnel mechanism so that the memory cell threshold voltage shifts to a low value (for instance 1 volt).
The write operation of the non-volatile semiconductor memory device of the prior art is explained by using FIG. 10. During the data read, the address Y corresponding to the latches LA0-LA3 are selected in succession, data corresponding to the selected address is applied to the data input line and data is set in the respective latches. At the same time, the input of the inverter comprised of P channel MOS transistor 58 and N channel MOS transistor 59 is pulled down to zero volts with the write signal PRO0 at HIGH so that the output sets to high (Vpp) and the N channel MOS transistor 61 turns on. Further, switching the write voltage VH to zero volts, initializes the bit lines BL0-BL3 setting a voltage potential of zero volts.
In initializing the bit line to zero volts, when the previous writing has been performed and the bit is held at a high potential (for instance 5 volts) as shown by the broken line in FIG. 10, the high potential (for instance 5 volts) is maintained even during the write interval and the memory cells (M01, M03) on which writing are not being performed are also set to write status so that writing errors are prevented. These writing errors are particularly prone to occur in memory cells written by the F-N tunnel mechanism at an extremely low write current (for instance 1 pico ampere).
Next, during data writing, the write signal PRO0 changes from HIGH level to LOW level and the signal PRO changes from LOW level to HIGH level. Further, the voltage VH changes from a low voltage to high voltage (e.g., 5 V). Therefore, each voltage corresponding to the data for each bit lines (in this example BL0=BL2=5 volts, BL1=BL3=0 volts) is applied to the respective bit lines, the target data is written by the F-N tunnel mechanism with -10 volts applied to the word lines (in this example WL0) selected by the X decoder 4 and a zero volt bias applied to the other non-selected word lines (in this example WL1 to WL3). In the example here, the threshold voltage for memory cells M00 and M02 shifts to a low value (for instance 1 volt) and the threshold voltage for memory cells M01 and M03 is maintained at a high value (for instance 6 volts) in erase status.
As shown in the prior art in FIG. 9, the gate of the transistor 61 is driven by the output signal from the latch 7 and a high voltage VH is applied to the bit line when the N channel MOS transistor 61 turn on because the data "1" is written in the latch 7. That is, when the N channel MOS transistor 61 turns off because the data "0" is latched in the latch 7, the bit lines are in a floating state, with the voltage potential of the initialized bit lines maintained at a voltage of zero volts. In such cases, since the bit lines are in a floating state, when the bit line voltage potential rises due to noise as for instance shown by the phantom lines of the bit line BL1 in FIG. 10, the prior art has the drawback that a "0" was written by mistake since a high voltage was maintained due to the extremely low write current.
Another problem in the prior art is the initialization interval needed for changing the bit line to zero volts as shown in FIG. 10. Here, the write voltage VH must be changed from the original voltage (for instance 5 volts) to a voltage of zero volts for initialization. This step requires providing a circuit to switch write voltages and voltages for performing initialization.